This document introduces a methodology for creating behavioral models of integrated circuit (IC) inputs and outputs and electrostatic discharge (ESD) protection devices for use in the simulation of ESD events that strike external connections of electronic systems. These models provide a framework for ESD simulation without revealing proprietary information about the components and provide a method for exchanging information between component manufacturers and original equipment manufacturers (OEM).

This document focuses on hard failures and quasi-static behavioral models. Hard failures are those caused by physical damage. In the future, these models may prove useful in the analysis of soft failures – failures due to system upset with no permanent damage.

Behavioral models mathematically describe a component without an underlying physical understanding of the device. Quasi-static models describe the current versus voltage characteristics after initial transients and device turn-on but before self-heating. A future TR will address the implementation of these models into the design flow.

System level ESD design is probably the most difficult design issue in the ESD field. As discussed below, the ESD robustness of an electronic system (including hard and soft failures) depends on many variables. These include properties of integrated circuits, protection devices and passive components, printed circuit board (PCB) design and layout, design and material of the enclosure, and software issues such as protocols, self-correction, and redundancy. ESD threats can come from many directions, as people and objects become charged and discharged to or near the electronic system. Data ports such as USB and HDMI are important entry points for ESD stress. An ESD event can occur when a cable is plugged in or, more likely, when the cable conducts an ESD event into the system. Therefore, understanding the propagation of an ESD stress from an external connector into a system and potentially sensitive integrated circuits is an important component in system level ESD design.

Electronic systems are tested for ESD robustness with IEC 61000-4-2 [1] or automotive products with ISO 10605 [2]. These test standards focus on ESD to enclosures and points of human contact; however, most OEMs also perform discharges to external connections. ESD failures for this type of stress are a serious concern for ICs, ESD protection devices, and system manufacturers.

The Industry Council on ESD Target Levels proposed a simulation methodology to address ESD threats to external connectors - system-efficient ESD design (SEED) [3]. In SEED, device models for all components on the ESD stress path into the system are developed, valid in the voltage, current, and time domain of an ESD threat. These models can then be used in a circuit simulator, such as SPICE, to predict circuit behavior during an ESD event. The subjects in this document are important elements of SEED.