The use of simulation in the design of electronic systems for ESD robustness has increased in the last several years, encouraged by the introduction of the SEED concept by the Industry Council on ESD Target Levels. The key to a successful simulation of ESD events is the model files of components in the ESD discharge path. Manufacturers of electronic components, such as integrated circuits and transient voltage suppressors (TVS), typically do not provide model files that describe device behavior in the ESD time and current domain. This document addresses how to create simple, quasistatic model files that describe the basic properties of electronic components appropriate for system-level ESD simulation.
The behavior of electronic components in the system level ESD time regime (tens of ns) and current (up to tens of amperes) domain is typically measured with transmission line pulse (TLP) systems. TLP systems stress the device under test with square wave pulses, typically 100 ns long, and measure the current through the device and voltage across the device during the pulse. Although transient measurements can be obtained, the most common output of a TLP system is a quasistatic I-V curve measured late in the TLP pulse that often averages over a measurement window of 70 ns to 90 ns. Quasistatic TLP I-V curves are the starting point for the model files developed in this document.
As quasistatic models for system-level modeling are intended to replicate the TLP I-V behavior, TLP is the only instrument required to measure the device characteristics. Generally, the voltage drop across the device is considered a function of the current only. Transient voltage overshoots inside the device are not considered. The I-V curve of the model depends upon the measured TLP results, which may have a variety of characteristics, including changes in resistance, breakdown voltages, snapback points, holding current, and voltage. Therefore, the modeling methodology should be general and should be able to be applied to more than one type of device. Most of the methods presented in this document achieve such generality by representing the device as a series of piecewise linear segments, as shown in Figure 1.